A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 27 (2019-11-01), S. 2620-2628
Online
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Zugriff:
The majority logic (ML) gate (MLG) is required in fast decoder implementations to protect memories from transient soft errors. In this paper, a novel MLG design is proposed; it consists of a pMOS pull-up network, an nMOS pull-down network, and an inverter. The proposed design is applicable to an arbitrary number of inputs $\gamma $ (and operating as a mirror circuit when $\gamma $ is odd). The proposed designs are simply requiring a small number of transistors; when simulated, they offer improved metrics such as reduction in delay, area, and power dissipation compared with existing designs found in the technical literature. When the combined power-delay-area product (PDAP) is considered, the advantages of the proposed designs are pronounced. The application of the proposed MLGs to design fast decoders for one-step ML decodable (OS-MLD) codes is also presented; the results show that the proposed MLGs are very efficient circuits for this coding application.
Titel: |
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes
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Autor/in / Beteiligte Person: | Guo, Jing ; Liu, Shanshan ; Zhu, Lei ; Lombardi, Fabrizio |
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Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 27 (2019-11-01), S. 2620-2628 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2019 |
Medientyp: | unknown |
ISSN: | 1557-9999 (print) ; 1063-8210 (print) |
DOI: | 10.1109/tvlsi.2019.2924721 |
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