Challenge and prospects for silicon SET/FET hybrid circuits

Si SET devices are discussed from the viewpoint of suitability for CMOS technology. Since there are limitations in the application of devices with a low driving performance and no gain in the conventional circuit scheme, it is a challenge to implement their advantages into a chip for better performance as a total system. We propose a quantum function-embedded CMOS structure that should be open for the implementation of new devices. A key point is a graceful assimilation, since a sudden change in the architecture is not a solution at present. Although Si device/process technology will certainly be developed further, continuing investigation of the SET technology is necessary, if the CMOS technology is to extend into the 21st century, down to the sub-50 nm level.