A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology
In: International Journal of Circuits, Systems and Signal Processing, Jg. 15 (2021-06-29), S. 556-568
Online
unknown
Zugriff:
The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.
Titel: |
A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology
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Autor/in / Beteiligte Person: | Shetty, Chaya ; Venkatesh Nuthan Prasad ; Nagabushanam, M. |
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Zeitschrift: | International Journal of Circuits, Systems and Signal Processing, Jg. 15 (2021-06-29), S. 556-568 |
Veröffentlichung: | North Atlantic University Union (NAUN), 2021 |
Medientyp: | unknown |
ISSN: | 1998-4464 (print) |
DOI: | 10.46300/9106.2021.15.62 |
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