Integration of NEMS resonators in a 65nm CMOS technology
In: Microelectronic Engineering, Jg. 110 (2013-10-01), S. 246-249
Online
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Zugriff:
In this work we study the feasibility to obtain the smallest CMOS-NEMS resonator using a sub-100nm CMOS technology. The NEMS resonators are defined in a top-down approach using the available layers of the 65nm CMOS technology from ST Microelectronics. A combination of dry and wet etching is developed in order to release the NEMS in an in-house post-CMOS process. Two different NEMS resonators are designed: 60nmx100nm polysilicon and 90nmx180nm copper clamped-clamped beams. The designed polysilicon CC Beam with a length of [email protected], resonates at 232MHz and is capable to provide the same mass sensitivity than a bottom-up silicon nanowire.
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Integration of NEMS resonators in a 65nm CMOS technology
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Autor/in / Beteiligte Person: | Giner, J. ; Marigo, E. ; Uranga, Arantxa ; Esteve, Jaume ; Muñoz-Gamarra, J. L. ; Barniol, Nuria ; Alcaine, P. |
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Zeitschrift: | Microelectronic Engineering, Jg. 110 (2013-10-01), S. 246-249 |
Veröffentlichung: | Elsevier BV, 2013 |
Medientyp: | unknown |
ISSN: | 0167-9317 (print) |
DOI: | 10.1016/j.mee.2013.01.038 |
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