Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design
In: IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 68 (2021-12-01), S. 4993-5006
Online
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Zugriff:
The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.
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Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design
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Autor/in / Beteiligte Person: | Roberts, Gordon W. ; Mohammed, Mahmood A. |
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Zeitschrift: | IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 68 (2021-12-01), S. 4993-5006 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 1558-0806 (print) ; 1549-8328 (print) |
DOI: | 10.1109/tcsi.2021.3110106 |
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