A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter
In: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Jg. 46 (1999-05-01), S. 507-516
Online
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Zugriff:
This paper presents a high-speed high-resolution low-power CMOS switched-current cyclic analog-to-digital converter (ADC). The high performance is attributed to the use of the following components: (1) a high-performance residual amplifier which takes two clock cycles to double a current; and (2) an efficient cyclic redundant signed-digit algorithm which provides 1.5 bit resolution without using two matched reference currents. Simulation results show that the developed ADC achieves 12-bit resolution and a conversion rate of 100 ns/bit, where the low-cost MOSIS SCAN20 2 /spl mu/m CMOS process and 3.3 V supply voltage are employed. The converter has been fabricated and tested, Experimental results on the test chip are also presented. The test chip achieves 12 bit resolution with differential nonlinearity of 0.6 LSB and the integral nonlinearity of 0.5 LSB when operated at a 0.8 Msample/s conversion rate. The power consumption is 1.9 mW.
Titel: |
A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter
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Autor/in / Beteiligte Person: | Wang, Jin-Sheng ; Wey, Chin-Long |
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Zeitschrift: | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Jg. 46 (1999-05-01), S. 507-516 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 1999 |
Medientyp: | unknown |
ISSN: | 1057-7130 (print) |
DOI: | 10.1109/82.769799 |
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