Area efficient layout design of CMOS circuit for high-density ICs
In: International Journal of Electronics, Jg. 105 (2017-06-21), S. 73-87
Online
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Zugriff:
Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any othe...
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Area efficient layout design of CMOS circuit for high-density ICs
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Autor/in / Beteiligte Person: | Vimal Kumar Mishra ; Chauhan, R. K. |
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Zeitschrift: | International Journal of Electronics, Jg. 105 (2017-06-21), S. 73-87 |
Veröffentlichung: | Informa UK Limited, 2017 |
Medientyp: | unknown |
ISSN: | 1362-3060 (print) ; 0020-7217 (print) |
DOI: | 10.1080/00207217.2017.1340978 |
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