INDEP approach for leakage reduction in nanoscale CMOS circuits
In: International Journal of Electronics, Jg. 102 (2014-03-11), S. 200-215
Online
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Zugriff:
Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the l...
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INDEP approach for leakage reduction in nanoscale CMOS circuits
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Autor/in / Beteiligte Person: | Raj, Balwinder ; Pattanaik, Manisha ; Vijay Kumar Sharma |
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Zeitschrift: | International Journal of Electronics, Jg. 102 (2014-03-11), S. 200-215 |
Veröffentlichung: | Informa UK Limited, 2014 |
Medientyp: | unknown |
ISSN: | 1362-3060 (print) ; 0020-7217 (print) |
DOI: | 10.1080/00207217.2014.896042 |
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