Design and Implementation of a Novel Boundary-Scan Circuit in FPGA’s Chip

This chapter presents a novel Boundary-Scan circuit compatible with IEEE1149.1 standard in a field-programmable gate array (FPGA). The novel Boundary-Scan circuit not only facilitates the chip test as well as an assembled printed circuit board (PCB) test but also severs as the configuration and verification of FPGA. This circuit is designed based on the configurable feature of FPGA. In this design, the boundary-scan chain can be configured to any desired length, which can efficiently improve the effective test speed. Also, a configurable scan chain controlled by the novel Boundary-Scan circuit can be flexibly formed in the FPGA core from which the controllability and observability of internal signals in the FPGA core are largely enhanced but not increase the overhead design. Besides, the conventional INTEST of Joint Test Action Group (JTAG) can be extended from single-step logic to multiple-step logic by connecting JTAG test clk input (TCK) signal into the test logic of FPGA core. The novel Boundary-Scan circuit has been implemented in an static random access memory (SRAM) based FPGA fabricated by a 0.5 µm silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The test results from the fabricated chip indicate that this circuit successfully realizes the desired functions in programming, verification, and testing.