Design of Ka band Low Noise Amplifier Based on 65nm CMOS Technology
In: 2021 International Applied Computational Electromagnetics Society (ACES-China) Symposium, 2021-07-28
Online
unknown
Zugriff:
In this paper, A Ka band low noise amplifier (LNA) using techniques of transformer matching and cross-coupling capacitance is designed using 65nm CMOS technology, the operating band covers 28-40GHz. The measured results show that this LNA consumes 14.2 mW under 1V, and high performances are achieved with the gain of 7.1 dB, noise figure(NF) of 5.9 dB, and the input 1dB compression point(P 1dB ) of −2.3 dBm. The chip occupies a silicon area of $320 \mu \mathrm{m}\times 280\, \mu \mathrm{m}$ .
Titel: |
Design of Ka band Low Noise Amplifier Based on 65nm CMOS Technology
|
---|---|
Autor/in / Beteiligte Person: | Wu, Shiwei ; Pang, Dongwei ; Liang, Xiangyu ; Sun, Liguo |
Link: | |
Zeitschrift: | 2021 International Applied Computational Electromagnetics Society (ACES-China) Symposium, 2021-07-28 |
Veröffentlichung: | IEEE, 2021 |
Medientyp: | unknown |
DOI: | 10.23919/aces-china52398.2021.9581351 |
Schlagwort: |
|
Sonstiges: |
|