Low-power VLSI design of arithmetic and logic circuits using the multiple-threshold CMOS technique
In: Smart Computing ISBN: 9781003167488; (2021-06-18)
Online
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Zugriff:
An exponential increase in the transistor density on a single substrate in an integrated circuit has paved the way for tremendous growth in the semiconductor industry. Very Large-Scale Integration (VLSI) of these transistors on a single substrate boosts performance, but also causes multiple issues related to delay and power consumption. It is important to boost performance but keep the trade-offs related to delay and power to a minimum. This has resulted in researchers moving towards low-power design techniques. Such techniques are different from conventional design techniques in such a way that power is consumed as and when needed. This helps in minimizing the total power consumed by any circuit. The aim of the work presented in this paper is to demonstrate the capability of the multiple-threshold complementary metal oxide semiconductor (MTCMOS) technique to achieve low power consumption with approximately same delay time in a single circuit. Standard arithmetic and logical circuits have been simulated at the 45 nm technology node and critical parameters, namely power and delay have been calculated using the MTCMOS technique and compared with conventional CMOS design. It is shown by studying some elementary yet frequently used circuits that by using transistors of different threshold levels (as in MTCMOS technique) power consumption is significantly reduced.
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Low-power VLSI design of arithmetic and logic circuits using the multiple-threshold CMOS technique
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Autor/in / Beteiligte Person: | Kataria, Prachi ; Anand, Ashwin ; Kapoor, Raman ; Singh, Sanjay ; Singh, Aanchal ; Rai, Anuwarti |
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Quelle: | Smart Computing ISBN: 9781003167488; (2021-06-18) |
Veröffentlichung: | CRC Press, 2021 |
Medientyp: | unknown |
ISBN: | 978-1-003-16748-8 (print) |
DOI: | 10.1201/9781003167488-78 |
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