A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme
In: Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94, 2002-12-17
Online
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Zugriff:
A 3.3 V single-power-supply 64 Mb (4M words x 16b) flash memory with a dynamic bit-line latch (DBL) programming has 50 ns access time and 256 b erase/programming unit-capacity using hierarchical word- and bit-line structures and DBL programming. This memory is fabricated using a 0.4 /spl mu/m-design-rule, double-layer-aluminum, triple-layer-polysilicon, twin-well CMOS technology. To reduce operating voltage, a high-capacitive-coupling ratio (HiCR) cell with high coupling ratio between the control gate and the floating gate is used. >
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A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme
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Autor/in / Beteiligte Person: | Takeshima, Toshio ; Hisamune, Yosiaki S. ; Sasaki, I. ; Murotani, T. ; Kanamori, Kohji ; Okazawa, Takeshi ; Sugawara, Hiroshi ; Takada, Hiroshi |
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Zeitschrift: | Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94, 2002-12-17 |
Veröffentlichung: | IEEE, 2002 |
Medientyp: | unknown |
DOI: | 10.1109/isscc.1994.344693 |
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