Logic Style Comparison for Ultra Low Power Operation in 65nm Technology

Design considerations for ultra low power circuits are presented through a study of circuit families operating at ultra low supply voltages. We examine static CMOS logic versus pass-transistor logic to determine which logic style is best suited for ultra-low power design. Furthermore, in this work we present a modification to Complementary Pass-gate Logic which improves its operation in ultra low power conditions. The operation of this modified CPL (MTCPL), in ultra low supply voltage conditions is compared to CMOS+, Dual Value Pass transistor Logic, and static CMOS in the same environment. The results show that although CMOS+ demonstrates the best energy delay characteristics for ultra low-power design, MTCPL yields the best energy at low data activities.