2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations

A 2[Formula: see text]VDD CMOS output buffer with process, voltage and leakage (PVL) detection mechanism is proposed such that slew rate is auto-adjusted to reduce the variations at different corners. To boost the driving current, low threshold voltage transistors are used instead of devices with typical threshold voltage in the driving transistor of output stage. More importantly, to prevent large leakage of those large low threshold voltage devices, leakage detection resistors are added at the gates of the always-on low threshold voltage transistors to clamp the leakage. The static power consumption is reduced when it is not activated. Another feature of the proposed design is that the gate-oxide leakage is also reduced by lengthening the driving transistors. Besides, all biases in the proposed design are generated from bandgap circuits such that not only is the variation caused by temperature drifting reduced, the area overhead and power dissipation are also minimized. The proposed design is carried out by using 28-nm CMOS process. The data rate proved by physical measurement is proved to be 2.0[Formula: see text]GHz given 1.8/1.05[Formula: see text]V supply voltage, namely, VDD or 2[Formula: see text]VDD, when the proposed PVL detection as well as the compensation circuitry are activated.