Design of 1 V switched-current cells in standard CMOS process
In: 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2002-11-07
Online
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Zugriff:
The minimum supply voltage for a typical switched-current (SI) cell can be shown to be greater than 2V/sub T/+2V/sub DSsat/ approximately due to the fact that an additional voltage drop is required for the MOS switch, which is connected to the gate of the memory transistor. Thus, a minimum supply voltage of 1.5 V is usually required in a standard CMOS process. In this paper, an active switching scheme is proposed for designing SI cells. The minimum supply voltage is equal to V/sub T/+2V/sub DSsat/. As a result, 1 V SI cells that exhibit low charge injection errors can be achieved.
Titel: |
Design of 1 V switched-current cells in standard CMOS process
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Autor/in / Beteiligte Person: | Lee, E.K.F. ; Rout, Saroj |
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Zeitschrift: | 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2002-11-07 |
Veröffentlichung: | Presses Polytech. Univ. Romandes, 2002 |
Medientyp: | unknown |
DOI: | 10.1109/iscas.2000.856354 |
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