4‐channel 35 Gbit/s parallel CMOS LDD
In: Electronics Letters, Jg. 51 (2015-07-01), S. 1178-1180
Online
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Zugriff:
The design of a 4-channel 35 Gbit/s parallel laser diode driver (LDD) using 65 nm CMOS technology is presented. The LDD driver consists of an input buffer stage, a pre-amplifier stage and an output driver stage. The three-stage cascaded amplifiers constitute the pre-amplifier stage, and an active feedback technique is employed to expand bandwidth without consuming a large area. The output driver stage introduces RC negative feedback and inductive shunt peaking techniques to broaden the bandwidth. Measurement results show that the operating rate of each channel is up to 35 Gbit/s and the power consumption per data rate is only 4.4 mW/(Gbit/s).
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4‐channel 35 Gbit/s parallel CMOS LDD
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| Autor/in / Beteiligte Person: | Gong, Jianwei ; Tian, Ling ; Chen, Yingmei ; Yao, Jianguo |
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| Zeitschrift: | Electronics Letters, Jg. 51 (2015-07-01), S. 1178-1180 |
| Veröffentlichung: | Institution of Engineering and Technology (IET), 2015 |
| Medientyp: | unknown |
| ISSN: | 1350-911X (print) ; 0013-5194 (print) |
| DOI: | 10.1049/el.2015.0885 |
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