Design of FPGA-Based QPP Interleaver for LTE/LTE-Advanced Application

Modern wireless communication systems have witnessed increasing use of channel coding techniques to enhance the throughput and to reduce latency. Interleavers are playing an important role to make the communication systems more robust and resilient in such channel coding approaches. The Long-Term Evolution (LTE)/LTE-Advanced of the 3rd Generation Partnership Project (3GPP) uses Quadrature Permutation Polynomial (QPP) interleaver in its Turbo coding scheme. The address generator of the interleaver contains a quadratic expression having square and modulus function whose direct digital hardware is not yet available in the literature. A novel algorithm has now been proposed which can provide low complexity hardware solution to implement the interleaver address generator. This paper describes VHDL model and timing simulation of the proposed address generator using ModelSim XE-III software. Due to absence of implementation results in the literature, comparison of this work is made by implementing conventional LUT-based technique on the same FPGA. Such comparison shows better FPGA resource utilization by 71.16% and improved operating speed by 82.26% in favour of the novel proposed technique.