Optimization of lateral double-diffused MOS transistors in 0.18 µm bipolar-CMOS-DMOS technology for wide-voltage applications

The reduced-surface-field-type lateral double-diffused MOS (LDMOS) structure, which is the key element used in the power device of the bipolar-CMOS-DMOS (BCD) process, was optimized for a wide voltage range of 20–60 V class in the 0.18 µm BCD process. The on-state resistance (Ron) characteristics to the drain-to-source breakdown voltage (BVdss) have been improved by optimizing the n-drift conditions and related design rules and the reliable safe operating area (SOA) of the device has also been secured for the 20–30 V class LDMOS device. In order to optimize the 40–60 V class LDMOS device, the n-drift drain buffer and low voltage-threshold voltage for the p-channel device implant were introduced and the reliable SOA was obtained while the excellent Ron characteristics showed up to the 60 V class. The final trade-off (Ron versus BVdss) characteristics of the LDMOS fabricated under the newly proposed 0.18 µm BCD process have shown competitive characteristics in the wide voltage range for the various applications.