A low power CMOS compatible embedded EEPROM for passive RFID tag
In: Microelectronics Journal, Jg. 41 (2010-10-01), S. 662-668
Online
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Zugriff:
A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18@mm CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018mm^2 and consumes 14.5 and 370@mW for read and write at 85^oC, respectively.
Titel: |
A low power CMOS compatible embedded EEPROM for passive RFID tag
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Autor/in / Beteiligte Person: | Kwon, Kee-Won ; Lee, Kyoung-Su ; Chun, Jung-Hoon |
Link: | |
Zeitschrift: | Microelectronics Journal, Jg. 41 (2010-10-01), S. 662-668 |
Veröffentlichung: | Elsevier BV, 2010 |
Medientyp: | unknown |
ISSN: | 0026-2692 (print) |
DOI: | 10.1016/j.mejo.2010.06.006 |
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