An LDE-Aware g m /I D -Based Hybrid Sizing Method for Analog Integrated Circuits
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 40 (2021-08-01), S. 1511-1524
Online
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Zugriff:
Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this article, a two-phase hybrid sizing method for high-performance analog circuits is proposed. It consists of $g_{m}$ / $I_{D}$ -based device characterization, circuit modeling, sensitivity-based constraints for LDEs, mixed-integer nonlinear programming (MINLP) in the first phase, and many-objective evolutionary algorithm (many-OEA)-based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the $g_{m}$ / $I_{D}$ design methodology. Then, the LDE parameters that are linked to the normalized dc current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many-OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floorplan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.
Titel: |
An LDE-Aware g m /I D -Based Hybrid Sizing Method for Analog Integrated Circuits
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Autor/in / Beteiligte Person: | Liao, Tuotian ; Zhang, Lihong |
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Zeitschrift: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 40 (2021-08-01), S. 1511-1524 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 1937-4151 (print) ; 0278-0070 (print) |
DOI: | 10.1109/tcad.2020.3025068 |
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