65-nm CMOS Voltage-to-Time Converter for 5-GS/s Time-Based ADCs

This paper discusses a voltage-to-time converter (VTC) designed for use in a time-based analog-to-digital converter. The VTC considered in this work is based on a starved-inverter topology. Linearity, delay, and jitter of the VTC are analyzed to facilitate a physical understanding of the circuit performance. The design is experimentally verified in a 65-nm CMOS technology. Measurement results show that the VTC, operating with a 5-GHz clock, has an output delay range of $$\pm 25\,{\text{ ps }}$$±25ps, 4.4 effective number of bits (ENOB), and output jitter of $$0.5\,\text{ ps }$$0.5ps RMS while consuming 4 mW of power. The input effective resolution bandwidth (ERBW) of the VTC is measured to be 4.1 GHz, over which the ENOB remains above 3.5 bits. The same VTC, operating with a 7.5-GHz clock, consumes 9.7 mW of power from a 1.2-V supply, has ENOB of >3.8 bits, ERBW of >7 GHz, output jitter of $$0.4\,\text{ ps }$$0.4ps RMS, and output delay range of $$\pm 25\,\text{ ps }$$±25ps. The VTC achieves the widest input bandwidth of any VTC reported to date.