Advanced Optical Testing of an Array in 65 nm CMOS Technology
In: International Symposium for Testing and Failure Analysis, 2005-10-01
Online
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Zugriff:
In this paper we present the advanced optical testing of an array fabricated in IBM’s 65 nm SOI CMOS technology, using the Picosecond Imaging Circuit Analysis (PICA) [1-11] tool equipped with the Superconducting Single-Photon Detector (SSPD) [12,13]. Based on the results of the optical analysis we were able to confirm a time collision problem in the readout circuit of the array. In the following sections we will also discuss the use of an innovative optical packaging for testing chips requiring wire-bonding, along with record low voltage optical measurements, down to 0.7 V.
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Advanced Optical Testing of an Array in 65 nm CMOS Technology
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Autor/in / Beteiligte Person: | Song, Peilin ; Christensen, Todd A. ; Stellari, Franco |
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Zeitschrift: | International Symposium for Testing and Failure Analysis, 2005-10-01 |
Veröffentlichung: | ASM International, 2005 |
Medientyp: | unknown |
ISSN: | 0890-1740 (print) |
DOI: | 10.31399/asm.cp.istfa2005p0355 |
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