Correlated jitter sampling for jitter cancellation in pipelined TDC
In: 2012 IEEE International Symposium on Circuits and Systems, 2012-05-01
Online
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Zugriff:
In this paper, the Correlated Jitter Sampling (CJS) technique, which alleviates the jitter induced error from the time reference in pipelined Time-to-Digital Converter (TDC), is proposed. The auxiliary pipelined TDC is employed to remove the jitter induced error of the main pipelined TDC in the CJS technique. A 12b pipelined TDC adopting the CJS technique in the 1st time quantization stage is simulated to validate the proposed technique. Simulation results show that the TDC can achieve a flat SNDR performance of 70dB regardless of the jitter from time reference up to 25% jitter of 1T LSB in reference clock, which is the maximum error allowed within a designed redundancy range of the pipelined TDC.
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Correlated jitter sampling for jitter cancellation in pipelined TDC
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Autor/in / Beteiligte Person: | Venkatram, Hariprasath ; Guerber, Jon ; Oh, Taehwan ; Moon, Un-Ku |
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Zeitschrift: | 2012 IEEE International Symposium on Circuits and Systems, 2012-05-01 |
Veröffentlichung: | IEEE, 2012 |
Medientyp: | unknown |
DOI: | 10.1109/iscas.2012.6272164 |
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