A compact low-power flash ADC using auto-zeroing with capacitor averaging
In: 2013 IEEE International Conference of Electron Devices and Solid-state Circuits, 2013-06-01
Online
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Zugriff:
This paper proposes efficient methods to reduce the cost and power consumption of flash analog-to-digital converters (ADCs). An auto-zeroing technique is incorporated with a low-complexity low-power capacitor averaging network for efficient offset cancellation and signal interpolation. Therefore, the cost and power consumption of flash ADCs can be efficiently reduced. A compact low-power 8-bit 500MS/s flash ADC with the above features is fabricated with 0.18μm CMOS process. The active area occupies 0.35mm2 and its measured power at 500MS/s is 160mW from a 1.8V supply. Measured signal-to-noise-plus-distortion ratio (SNDR) of the ADC is 40dB with 200MHz input frequency sampled at 500MS/s. The figure-of-merit (FOM) is 4.17pJ/conversion-step, which is the best compared to published 0.18μm 8-bit flash ADCs. Further, the power consumption and active area are the smallest compared with state-of-the-art 0.18μm 8-bit high-speed ADCs.
Titel: |
A compact low-power flash ADC using auto-zeroing with capacitor averaging
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Autor/in / Beteiligte Person: | Lee, Ching-Chung ; Yang, Chung-Ming ; Kuo, Tai-Haur |
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Zeitschrift: | 2013 IEEE International Conference of Electron Devices and Solid-state Circuits, 2013-06-01 |
Veröffentlichung: | IEEE, 2013 |
Medientyp: | unknown |
DOI: | 10.1109/edssc.2013.6628195 |
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