Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform
In: IEEE Electron Device Letters, Jg. 33 (2012-07-01), S. 934-936
Online
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Zugriff:
In this letter, we investigate the effect of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the effect of source-drain extension (S/Dext) scaling and device asymmetry on device and circuit performances for 15 nm VNW CMOS. It is seen that, due to reduced series resistance, circuit delay continues to improve with S/Dext down to 10 nm, despite increased parasitic capacitances. Also, we show that asymmetry between top and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by 65% with top electrode as source, which is attributed to increase in series resistance and gate-drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40% delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.
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Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform
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Autor/in / Beteiligte Person: | Singh, Navab ; Kaushal, Gaurav ; Anand, Bulusu ; Maheshwaram, S. ; Sanjeev Kumar Manhas |
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Zeitschrift: | IEEE Electron Device Letters, Jg. 33 (2012-07-01), S. 934-936 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2012 |
Medientyp: | unknown |
ISSN: | 1558-0563 (print) ; 0741-3106 (print) |
DOI: | 10.1109/led.2012.2197592 |
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