A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process
In: International Journal of Circuit Theory and Applications, Jg. 43 (2014-03-05), S. 822-828
Online
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Zugriff:
A 5.25-V-tolerant bidirectional I/O circuit has been developed in a 28-nm standard complementary metal-oxide-semiconductor CMOS process with only 0.9 and 1.8V transistors. The transistors of the I/O circuit are protected from over-voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n-well bias level of the p-type metal-oxide-semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25-V-tolerant bidirectional I/O circuit occupies 40µm×170µm of silicon area. Copyright © 2014 John Wiley & Sons, Ltd.
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A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process
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Autor/in / Beteiligte Person: | Ahn, Keun-Seon ; Yoo, Changsik ; Park, Jaewoo |
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Zeitschrift: | International Journal of Circuit Theory and Applications, Jg. 43 (2014-03-05), S. 822-828 |
Veröffentlichung: | Wiley, 2014 |
Medientyp: | unknown |
ISSN: | 0098-9886 (print) |
DOI: | 10.1002/cta.1981 |
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