Characterization of Advanced Gate Architecture Stress on 22nm Gate-Last CMOS Device
In: ECS Transactions, Jg. 44 (2012-03-16), S. 779-784
Online
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Zugriff:
In this paper, the characteristics of gate strain enginnering on 22nm High-k/Metal-Gate-last (HK/MG-last) CMOS device are studied through a process and device simulation by Sentarus TCAD tools. In addition, we proposed novel gate electrode architecture with trapezoid profile and investigated its special strain effect on channel. We also proposed one new integration approach for stressed dummy gate fabrication.
Titel: |
Characterization of Advanced Gate Architecture Stress on 22nm Gate-Last CMOS Device
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Autor/in / Beteiligte Person: | Ma, Xiaolong ; Yin, Huaxiang ; Fu, Zuozhen |
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Zeitschrift: | ECS Transactions, Jg. 44 (2012-03-16), S. 779-784 |
Veröffentlichung: | The Electrochemical Society, 2012 |
Medientyp: | unknown |
ISSN: | 1938-6737 (print) ; 1938-5862 (print) |
DOI: | 10.1149/1.3694398 |
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