A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS
In: Journal of Semiconductors, Jg. 43 (2022-07-01), S. 072401-72401
Online
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Zugriff:
This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10−12 BER at 26 Gb/s for a 215−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.
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A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS
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Autor/in / Beteiligte Person: | Pan, Quan ; Luo, Xiongshi ; Li, Zhenghao ; Jia, Zhengzhe ; Chen, Fuzhan ; Ding, Xuewei ; C. Patrick Yue |
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Zeitschrift: | Journal of Semiconductors, Jg. 43 (2022-07-01), S. 072401-72401 |
Veröffentlichung: | IOP Publishing, 2022 |
Medientyp: | unknown |
ISSN: | 2058-6140 (print) ; 1674-4926 (print) |
DOI: | 10.1088/1674-4926/43/7/072401 |
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