A CMOS macro-model for MTJ resistor of MRAM cell
In: physica status solidi (a), Jg. 201 (2004-06-01), S. 1653-1657
Online
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Zugriff:
When a matured magneto-resistive random access memory (MRAM) process is not available, a CMOS macro-model for MRAM cell can be a good tool for developing efficient MRAM architectures and their competitive peripheral circuits. This paper proposes a novel CMOS modelling circuit emulating voltage-dependent characteristics of MTJ resistance in a 2T2MTJ cell and its applications in the MRAM full-chip. The variable resistance characteristic is realized by applying the feedback voltage to the gate of the MOS resistor. A test MRAM full-chip adopting the proposed model was implemented in a 0.35 μm CMOS process.
Titel: |
A CMOS macro-model for MTJ resistor of MRAM cell
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Autor/in / Beteiligte Person: | Kim, Daejeong ; Ju Hyun Ko ; Cho, Chung-Hyun |
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Zeitschrift: | physica status solidi (a), Jg. 201 (2004-06-01), S. 1653-1657 |
Veröffentlichung: | Wiley, 2004 |
Medientyp: | unknown |
ISSN: | 1521-396X (print) ; 0031-8965 (print) |
DOI: | 10.1002/pssa.200304613 |
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