Back-End-of-Line Compatible Fully Depleted CMOS Inverters Employing Ge p-FETs and α-InGaZnO n-FETs
In: IEEE Electron Device Letters, Jg. 42 (2021-10-01), S. 1488-1491
Online
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Zugriff:
In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ( $\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing ( SS ) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage ( ${V}_{\text {TH}}$ ), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V.
Titel: |
Back-End-of-Line Compatible Fully Depleted CMOS Inverters Employing Ge p-FETs and α-InGaZnO n-FETs
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Autor/in / Beteiligte Person: | Han, Kaizhen ; Wang, Chengkuan ; Gong, Xiao ; Zhou, Z. H. ; Kumar, Annie ; Zhou, Jiuren ; Kang, Yuye ; Sun, Chen |
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Zeitschrift: | IEEE Electron Device Letters, Jg. 42 (2021-10-01), S. 1488-1491 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 1558-0563 (print) ; 0741-3106 (print) |
DOI: | 10.1109/led.2021.3109343 |
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