Comparative Analysis of Modeling CMOS Majority Gates When Collecting a Charge from Tracks of Single Ionizing Particles

The two main variants of a CMOS Triple Majority Gate (TMG) for redundant computing systems used on exposure to single nuclear particles are modeled and compared. This is a variant on 2-input 2AND and 2OR logic gates and a variant on three 2-input 2AND gates and one 3-input 3OR gate. It is modeled using 3D TCAD tools, including the physical modeling of the linear energy transfer (LET) to the particle’s track. The transistors are made using 65-nm bulk silicon CMOS technology with shallow trench isolation (STI). The durations of the interference pulses at the outputs of the NAND, AND, NOR, and OR gates, the dependence of the duration on the pulse shape, and the duration of the delays from the moment the track appears to the moment when the pulse front rises to the threshold amplitude value with the dependence to the particle’s track in the range of 10 to 90 MeV cm2/mg are compared. Tracks with the direction normal to the crystal surface are used. The mechanism of reducing (correcting) the duration of the interference pulses at the outputs of the AND and OR gates with an increase in the dependence to the track is analyzed. Due to the correction effect, the duration of the interference pulses at the output of the AND gate, OR gate and, accordingly, at the TMG when collecting the charge from the track with the input point in the corresponding gate does not exceed 150 ps at the output of the 2AND gate; 50–100 ps, at the output of the 2OR gate; or 250–350 ps, at the output of the 3OR gate. The minimum interference duration is observed in the TMG version, performed only on 2-input AND and OR gates.