CMOS analog and mixed-signal phase-locked loops: An overview
In: Journal of Semiconductors, Jg. 41 (2020-11-01), S. 111402-111402
Online
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Zugriff:
CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.
Titel: |
CMOS analog and mixed-signal phase-locked loops: An overview
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Autor/in / Beteiligte Person: | Zhang, Zhao |
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Zeitschrift: | Journal of Semiconductors, Jg. 41 (2020-11-01), S. 111402-111402 |
Veröffentlichung: | IOP Publishing, 2020 |
Medientyp: | unknown |
ISSN: | 2058-6140 (print) ; 1674-4926 (print) |
DOI: | 10.1088/1674-4926/41/11/111402 |
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