This work is on the design of a fully integrated 0.13-µm CMOS multi-standard power constrained simultaneous noise and input matching low-noise amplifier (PCSNIM LNA). The multi-standard capability is obtained via the implementation of CMOS switches. The input and output matching are fully implemented on a chip, which is uncommon when compared to the existing multi-standard LNA topologies. The multi-standard LNA is operated at 0.9, 1.8, and 2.1 GHz frequencies. The design covered wireless standards of GSM900, DCS1800, and W-CDMA applications. The multi-standard LNA can obtain noise figure as low as 1.72 dB. The third-order intercept point, IIP3, is as high as −4 dBm, while IP1dB is −10 dBm. The power consumption of the design is only 7.4 mW. This resistorless multi-standard LNA design is not just able to operate at three different frequencies but also has a comparable performance with the rest. Its merits are contributed by high linearity and low power.
Keywords: DCS; GSM; Impedance matching; Inductively source degenerated LNA; Linearity; Multi-standard LNA; Noise figure; PCSNIM; S-parameters; W-CDMA
In the past few decades, wireless communication systems have steadily evolved and grown rapidly. Thus, such systems have high market demand. The functionality of radio frequency (RF) transceivers increases as RF designers pursue cost-effective multi-standard transceivers. Multi-band transceivers with wireless standards that can operate simultaneously are desirable to extend their functionalities [[
The last method is the tunable narrowband multi-standard LNA [[
The design of a multi-standard LNA is difficult because it has to provide functions, such as input matching at different frequencies, and satisfy different and interdependent specifications, such as low-noise figure (NF), high gain, and good linearity. These functions depend on the design parameters values to improve one function but consequently deteriorate the others. Several techniques and methods have been implemented and optimized to overcome the trade-offs in this LNA design.
This paper is organized as follows: Section 2 presents the design implementation of a narrowband, switching multi-standard LNA using CMOS switches. Section 3 discusses the equivalent input and output impedances of the cascode circuit at the three desired frequencies under the different switches' conditions. Section 4 presents measurement results of this multi-standard LNA while Section 5 concludes the findings of the work and the achievements' summary.
Figure 1 presents the schematic diagram of the multi-standard LNA circuit design used in this work. The LNA topology is based on CMOS switching to control the tuning circuitries, and the design is based on inductively degenerated power constrained simultaneous noise and input matching (PCSNIM) architecture LNA [[
Graph: Figure 1: Multi-standard LNA design for three frequencies
The CMOS switches enable the LNA to tune between the desired frequency bands, which are 0.9, 1.8, and 2.1 GHz. The design can be tuned to these frequencies by using switches M
The configuration of these switch transistors varies the LNA tuning frequency by changing the value of the passive elements [[
As can be seen in Figure 1, the multi-standard LNA design used in this work involves inductively sourced degenerated circuit concept.
Referring to Figure 2, the transistor is biased to operate in its triode region and display resistive I–V characteristic. The switch acts as a capacitor when turned off and as a resistor when it is on [[
Graph: Figure 2: (a) Switch; (b) NMOS as switch; (c) MOS is switched on; and (d) MOS is switched off
The circuit in Figure 1 has CMOS switches controlling the relevant tuning frequency according to the conditions as shown in Table 1. The switches are made to turn on and off at different frequencies.
Table 1: Switch condition
Switches 2.1 (GHz) 1.8 (GHz) 0.9 (GHz) Off Off On Off On Off On On Off Off On On
As stated previously, the multi-standard LNA is based on the inductively source degenerated PCSNIM topology. This topology comprises the best impedance matching in narrow-band operation compared with other architectures, such as folded cascode, common-gate, and common-source with shunt input amplifier [[
Figure 3 shows the schematic of a simple PCSNIM LNA, while Figure 4 is the small signal equivalent circuit of its input stage. The stability of this topology is good because the cascode architecture reduces the interaction between the output and input stages, enabling separate optimization, thus improving its reverse isolation. Inductively degenerated LNA provides the best noise performance because of the absence of resistors.
Graph: Figure 3: Simple PCSNIM LNA
Graph: Figure 4: Small signal equivalent circuit of input stage
The input impedance, Z
(
Graph
where C
Equation (
The LNA is initially designed to operate at the highest required centre frequency because the LNA can later be tuned to the lower frequencies just by adding extra passive components.
The Z
Graph
When switch is off, it can be represented by an open circuit. Vice versa, when the switch is on, it can be represented by a short circuit. The above C
Output matching circuit determines the output impedance Z
(
Graph
Equation (
In this section, the measurement results of the multi-standard LNA at 0.9, 1.8, and 2.1 GHz are presented. The results are for gain (S
Graph: Figure 5: Photomicrograph of the proposed multi-standard LNA
Figures 6–8 show the measurement results of power gain (S
Graph: Figure 6: S21 results
Graph: Figure 7: S11 results
Graph: Figure 8: S22 results
The S
This shows that the cascode is capable of providing good isolation. All of the results were obtained at a current of 6.2 mA.
Figure 9 shows the NF performance for the three frequency bands of operation [[
Graph: Figure 9: NF results
Figure 10 shows the measured I
Graph: Figure 10: IP1dB results
Graph: Figure 11: IIP3 results
Table 2: Comparison with previous works by others
Ref Freq (GHz) NF (dB) Power (mW) Remark [ 1.8 −11.52 na 14.54 −8.42 1.75 −16.00 −5.8 7.5 Measured 2.14 −15.18 na 16.6 −10.97 1.97 −14.80 −5.3 7.5 Off-chip [ 0.9 −12 na 13 −7 2.3 na −14 7.5 Measured 1.8 −14 na 12.6 −9 2.9 na −14 7.5 Off-chip 5.2 −12 na 14.2 −10 2.3 na −14 7.5 [ 1.6 −19 −57.6 16.2 −14.6 3.3 −2.2 −14 56 Simulated 1.8 −22.4 −56.1 16 −23.4 3.3 −3.3 −13.7 46.2 2.1 −28.5 −54.3 15.5 −34.2 3.5 −14 −13.5 31 2.4 −28.4 −53.8 15.5 −32 3.2 −14 −13.9 27 This 0.9 −9.1 −47 10.76 −14 4.3 −12.2 −1 7.4 Measured work 1.8 −14 −34.5 11.38 −23 1.72 −11.8 0.2 7.4 On-chip 2.1 −11.6 −48 10.26 −37.9 1.85 −11 −2 7.4
Table 2 summarizes the performance of the measured multi-standard LNA for performance metrics as compared with previous work. Previous works also adopt similar cascode structure [[
Resistive shunt feedback method was applied in [[
Balemarthy [[
In general, this work achieved better results compared to others as tabulated in Table 2.
A fully integrated 0.13-μm CMOS multi-standard switchable LNA was successfully designed to operate at 0.9, 1.8, and 2.1 GHz. The design consumed a very low current of 6.2 mA, corresponding to a 7.4 mW of power dissipation. The design exhibits 1.8/1.7/4.3 dB of NF at 0.9/1.8/2.1 GHz, more than |34| dB of reverse isolation, P1dB of as high as −11 dBm, and an IIP3 of as high as 0.2 dBm. This multi-band LNA is able to achieve a much better linearity and power consumption as compared to that of the other multi-band narrow-band LNAs of its kind. In general, this resistorless design is not just able to operate at three different frequencies but also has a comparable performance with the rest.
The authors would like to thank the Collaborative Micro-electronic Design Excellence Centre (CEDEC) for supporting Cadence EDA tools and Silterra (M) Sdn. Bhd. for the 0.13-µm CMOS model libraries. This work was supported by Collaborative Research in Engineering, Science and Technology (CREST) grant (grant number 304/PELECT/ 6050262/C121), and Postgraduate Research Grant Scheme (PRGS) (grant number 1001/PELECT/8034029).
No potential conflict of interest was reported by the authors.
By Awatif Hashim; Norlaili Mohd Noh; Shukri Korakkottil Kunhi Mohd; Yusman Mohd. Yusof; Mohd Haidar Hamzah; Mohd Tafir bin Mustaffa; Asrulnizam Abd Manaf and Othman Sidek
Reported by Author; Author; Author; Author; Author; Author; Author; Author
Awatif Hashim graduated in BEng (electronic) degree from Universiti Malaysia Perlis (UniMAP) in 2008. She has just finished her MSc study in analog integrated circuit design mainly based on low-noise amplifier design in Universiti Sains Malaysia (USM). Her working experiences are research assistant/research officer in USM and postgraduate intern in Silterra (M) Sdn. Bhd.E-mail:
Norlaili Mohd Noh received her BEng degree in electrical engineering from Universiti Teknologi Malaysia (UTM) in 1987, MSc and PhD degrees from Universiti Sains Malaysia (USM) in 1995 and 2009, respectively. She is currently a senior lecturer with the School of Electrical and Electronic Engineering USM. She was promoted to an associate professor in 2015. Her current research interests include low-noise amplifier design, analog circuit design, and radio frequency integrated circuit (RFIC) design.E-mail:
Shukri Korakkottil Kunhi Mohd graduated BEng (mechatronic) and MSc (electronic) degrees from Universiti Sains Malaysia (USM) in 2006 and 2011, respectively. Currently, he is pursuing doctoral postgraduate study as part time student in device modeling and characterization at USM. Besides that, he is working as a research officer at Collaborative Micro-Electronic Design Excellence Center (CEDEC), USM.E-mail:
Yusman Mohd. Yusof received his BEng degree in electronic and computer engineering from Universiti Putra Malaysia (UPM) in 1999. He is currently working at Silterra (M) Sdn. Bhd. focusing on devices characterization and models development including the radio frequency (RF) and electrostatic discharge (ESD).E-mail:
Mohd Haidar Hamzah received B Eng degree from University Technology Mara (UiTM), Malaysia in 2007. He received MSc degree from University Technology Malaysia (UTM), Malaysia in 2010. From 2007 to 2012, he worked as a hardware validation engineer and physical layout design engineer at Intel Malaysia. He was a CAD senior engineer in Design Technology Department, Silterra (M) Sdn. Bhd. from 2012 to 2013 and currently a device modeling engineer at SilTerra Malaysia.E-mail:
Mohd Tafir Mustaffa received his BEng degree in electrical and electronic engineering from Universiti Sains Malaysia (USM), Penang in 2000. He was awarded a master degree (MEngSc) in computer and microelectronic engineering from Victoria University, Australia in 2005 and was officially completed his PhD degree in electrical engineering specializing in radio frequency integrated circuit (RFIC) in September 2009. He served as a system engineer at Data Acquisition System (M) Sdn. Bhd and tutor in USM. He is now a senior lecturer at the School of Electrical and Electronic Engineering, USM, Engineering Campus. Dr Mohd Tafir Mustaffa is a member of IEEE, IET, and also a member of Advanced Integrated System Device, a group research at USM. He is actively involved with IEEE Circuits and Systems Society for the last few years as a committee member. He is the author and co-author of more than 30 technical papers in conferences and journals, book and book chapters. He is currently involved in the research of digital and analog IC, RFIC, and RF MEMS design.E-mail:
Asrulnizam Abd Manaf received B Eng and MSc degrees in electrical and electronic engineering from Toyohashi University of Technology, Japan in 2001 and 2005, respectively. He worked as an electrical engineer at the Toyo-Memory Technology Sdn. after completing his undergraduate study. He pursued his PhD study in Keio University, Japan in 2006. He received PhD in engineering from the Department of Applied Physic and Physico Informatics, School of Fundamental Science and Technology, in 2009. He joined the School of Electrical and Electronic Engineering, Universiti Sains Malaysia (USM) as a senior lecturer. He was promoted to an associate professor in 2015. He has authored and co-authored 60 international technical journals or conference papers. His current research interest includes development of microfluidic-based DNA sensor integrated with CMOS circuitry, miniaturized of fluidic-based inclination sensor, bio inspired based microfluidic acoustic, pressure and flow sensor for underwater system, micro fluidic-based memristor, micro Thermoelectric Generator (mTEG)-based energy harvesting, graphene-based transistor, and micro three-dimensional fabrication technique by using grayscale Technology.E-mail:
Othman Sidek graduated as bachelor of applied science (electronics) at Universiti Sains Malaysia (USM) in 1982 and awarded MSc degree in communication engineering from UMIST, Manchester in United Kingdom (UK) in 1984. Then he began serving as a lecturer at the School of Applied Science which was later renamed as School of Electrical & Electronic Engineering in 1986. Later, he went for his PhD degree and completed in information system engineering from Bradford University, UK in 1993. He has significant contribution in Malaysia's nation building efforts especially with the setting up of Collaborative μElectronic Design Excellence Centre (CEDEC) at USM, wherein he served as the founding director from 2007 to 2012. His research interests include: MEMS, micro and nano electronics, wireless sensor networks, embedded systems and SOC. He has been awarded numerous research grants, supervised dozens of postgraduate students and has worked on dozens of international publications. He also lectures a wide range of electronic engineering courses and invited keynote speakers locally and internationally.E-mail:
