A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS
In: Circuits, Systems, and Signal Processing, Jg. 40 (2021-01-21), S. 3125-3142
Online
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Zugriff:
This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm $$^{2}$$ area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.
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A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS
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Autor/in / Beteiligte Person: | Zhou, Jianjun ; Jin, Jing ; Guo, Yuekang ; Hu, Mengying ; Liu, Xiaoming |
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Zeitschrift: | Circuits, Systems, and Signal Processing, Jg. 40 (2021-01-21), S. 3125-3142 |
Veröffentlichung: | Springer Science and Business Media LLC, 2021 |
Medientyp: | unknown |
ISSN: | 1531-5878 (print) ; 0278-081X (print) |
DOI: | 10.1007/s00034-020-01643-z |
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