3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS
In: 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019-02-01
Online
unknown
Zugriff:
Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1–4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1–5].
Titel: |
3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS
|
---|---|
Autor/in / Beteiligte Person: | Juan Carlos Pena Ramos ; Verhelst, Marian ; Tavernier, Filip ; Strackx, Maarten ; J. M. Marcel Pelgrom ; Lyu, Yifan ; Steyaert, Michiel ; Ramkaj, Athanasios |
Link: | |
Zeitschrift: | 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019-02-01 |
Veröffentlichung: | IEEE, 2019 |
Medientyp: | unknown |
DOI: | 10.1109/isscc.2019.8662490 |
Schlagwort: |
|
Sonstiges: |
|