A study of gateless OTP cell using a 45nm CMOS compatible process
In: Solid-State Electronics, Jg. 53 (2009-10-01), S. 1092-1098
Online
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Zugriff:
This work proposes a new gateless one-time programmable (OTP) cell. This gateless OTP cell has a parasitic oxide–nitride–oxide (ONO) structure as the storage node and is successfully demonstrated in a 45 nm CMOS logic process. This gateless OTP cell, formed in a pure logic process and decoupled from gate oxide, is highly stable with a five orders of on/off current window. It also exhibits superior program performance, with an operating voltage of only 5 V and at a programming current of no more than 10 μA. Unlike breakdown-based anti-fuses, electron trapping of the gateless OTP cell demonstrates repeatability for testing. The gateless OTP can be UV-erased and is stable over 10 P/E cycles. An electrical erase mechanism with limited performance is also characterized and discussed. This new nitride gateless anti-fuse cell is a very promising logic OTP solution that provides fully compatibility to CMOS process below the 90 nm node.
Titel: |
A study of gateless OTP cell using a 45nm CMOS compatible process
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Autor/in / Beteiligte Person: | Chrong Jung Lin ; Shih, H. C. ; Chiu, Hsin-Yi ; Lin, Kai-Chun ; Tsai, Yi-Hung ; King, Ya-Chin |
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Zeitschrift: | Solid-State Electronics, Jg. 53 (2009-10-01), S. 1092-1098 |
Veröffentlichung: | Elsevier BV, 2009 |
Medientyp: | unknown |
ISSN: | 0038-1101 (print) |
DOI: | 10.1016/j.sse.2009.06.007 |
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