A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth

We describe the design principles and circuit details of a three-stage continuous-time pipeline (CTP) ADC that achieves 70-dB SNDR in a 100-MHz bandwidth while sampling at 800 MHz. Implemented in 65-nm CMOS, the ADC is easy to drive and incorporates an inherent anti-alias filter that achieves 60-dB rejection in the first Nyquist band. Each pipeline stage is realized using a second-order Rauch-filter-based residue amplifier that incorporates a 9-level resistive DAC and an RC-delay line. A dummy-switching scheme relaxes DAC reference-buffer requirements. The back-end ADC is a $4\times $ time-interleaved 7-bit SAR converter. The Schreier and Walden FoMs of our ADC are 165.4 dB and 56.1 fJ/level, respectively.