Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS
In: IEEE Transactions on Microwave Theory and Techniques, Jg. 64 (2016-04-01), S. 1143-1152
Online
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Zugriff:
This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.
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Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS
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Autor/in / Beteiligte Person: | Ellinger, Frank ; Tretter, Gregor ; Mohammad Mahdi Khafaji ; Carta, Corrado ; Fritsche, David |
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Zeitschrift: | IEEE Transactions on Microwave Theory and Techniques, Jg. 64 (2016-04-01), S. 1143-1152 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2016 |
Medientyp: | unknown |
ISSN: | 1557-9670 (print) ; 0018-9480 (print) |
DOI: | 10.1109/tmtt.2016.2529599 |
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