Floating gate analog implementation of the additive soft-input soft-output decoding algorithm
In: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2003-06-25
Online
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Zugriff:
The soft-input soft-output decoding algorithm is used to decode concatenated codes iteratively. To implement this algorithm efficiently, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.
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Floating gate analog implementation of the additive soft-input soft-output decoding algorithm
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Autor/in / Beteiligte Person: | Mondragon-Torres, Antonio F. ; Sanchez-Sinencio, Edgar |
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Zeitschrift: | 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2003-06-25 |
Veröffentlichung: | IEEE, 2003 |
Medientyp: | unknown |
DOI: | 10.1109/iscas.2002.1010931 |
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