Optimization, FPGA Implementation & CMOS Realization of Reversible Shift Registers

Recently reversible logic has emerged as one of the most important designs as it is known to provide zero power dissipation under ideal conditions. Reversible logic is used in the field of low power VLSI, nano technology, communications, high speed VLSI, digital signal processing etc. The optimization is carried out in reversible circuits by reducing gate count, constant inputs, garbage outputs as well as quantum cost. In this paper we are presenting the optimized designs of sequential circuits such as flip-flop and four types of shift registers in both FPGA implementation and CMOS implementation. In the cmos implementation we have used 180nm cmos technology in the design of shift registers. At final we obtained the results of power, delay and power delay product of shift registers using mosfet of 180nm technology.