An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <tex-math notation='LaTeX'>$0.175~\mu$ </tex-math> W/Channel in 65-nm CMOS
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 27 (2019), S. 126-137
Online
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Zugriff:
This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 $\mu \text{W}$ /channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2.
Titel: |
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <tex-math notation='LaTeX'>$0.175~\mu$ </tex-math> W/Channel in 65-nm CMOS
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Autor/in / Beteiligte Person: | Anh Tuan Do ; Seyed Mohammad Ali Zeinolabedin ; Jeon, Dongsuk ; Sylvester, Dennis ; Tony Tae-Hyoung Kim |
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Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 27 (2019), S. 126-137 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2019 |
Medientyp: | unknown |
ISSN: | 1557-9999 (print) ; 1063-8210 (print) |
DOI: | 10.1109/tvlsi.2018.2875934 |
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