An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 38 (2019-10-01), S. 1811-1819
Online
unknown
Zugriff:
An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog–digital interfaces. By implementing the sequential analog fabric, the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem—classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
Titel: |
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
|
---|---|
Autor/in / Beteiligte Person: | Du, Yuan ; Chen, Xiaoliang ; Du, Jieqiong ; Gu, Xuefeng ; Iyer, Subramanian S. ; Mau-Chung Frank Chang ; Ming-Zhe, Jiang ; Du, Li ; X. Shawn Wang ; Hu, Boyu |
Link: | |
Zeitschrift: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. 38 (2019-10-01), S. 1811-1819 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2019 |
Medientyp: | unknown |
ISSN: | 1937-4151 (print) ; 0278-0070 (print) |
DOI: | 10.1109/tcad.2018.2859237 |
Schlagwort: |
|
Sonstiges: |
|