A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model

Intensive scaling of Integrated Circuits is a crucial factor for achieving high performance and astronomical packing density. However, this scaling is pushing planar MOSFET to its physical limitations. Nowadays, FinFET emerges as a promising alternative technology for planar MOSFET, due to their better efficiency. Nevertheless, this inevitably leads to a rising concern on the reliability of FinFET as the circuit lifetime reliability cannot be neglected due to this accelerated scaling of Integrated Circuits. This paper is considered as the first work that: 1) detects which CMOS technology, planar MOSFET or FinFET, is more robust against Bias Temperature Instability (BTI) aging degradation for the advanced nodes such as 16 nm; 2) precisely computes the effect of BTI on 16 nm FinFET using an adequate BTI Reaction Diffusion model that takes into consideration the effects of finite oxide thickness, and the influence of polysilicon; 3) investigates the efficiency in terms of power consumption and area for the predominant circuit level techniques that could be implemented to overcome the negative impact of BTI for FinFET technology. This research clearly indicates that FinFET technology is more robust against BTI aging degradation than planar MOSFET as the delay percentage for FinFET technology is lower than planar MOSFET technology by 26%.