Design Techniques of Sub-ns Level Shifters With Ultrahigh dV/dt Immunity for Various Wide-Bandgap Applications
In: IEEE Transactions on Power Electronics, Jg. 36 (2021-09-01), S. 10447-10460
Online
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Zugriff:
In high-frequency gate drivers, especially for wide-bandgap applications, hundreds of voltages per nanosecond noise would be generated. Therefore, the sub-ns delay level shifter with high dV/dt immunity is necessary for signal conversion among different voltage domain areas. This article presents design techniques for the sub-ns delay level shifter with ultrahigh dV/dt immunity. The propagation delay of the proposed floating level shifter is dramatically reduced by utilizing the edge detection technique. In order to further improve the performance, auxiliary pull-up circuit, promoting delay matching, and self-calibration techniques are adopted, which make the proposed level shifters more suitable for high-frequency wide-bandgap applications. The level shifter is fabricated in a 0.5 μ m bipolar CMOS DMOS (BCD) process, whose results demonstrate the final level shifter achieves zero static power consumption, a 0.024 mm2 active area, and dV/dt immunity up to 250 V/ns. The measurement results show that the sub-ns delay level shifter can be realized, and the minimum delay is only 664 ps at VSSH 25 V. Its figure of merit is just 0.044 ns/( μ m × V), which is optimal among previous level shifters. The level shifters are also simulated at the 0.18 μ m BCD process, and the propagation delay can be decreased by more than 60%.
Titel: |
Design Techniques of Sub-ns Level Shifters With Ultrahigh dV/dt Immunity for Various Wide-Bandgap Applications
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Autor/in / Beteiligte Person: | Jianwen, Cao ; Tang, He ; Zhang, Bo ; Wang, Zhuo ; Zhou, Zekun |
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Zeitschrift: | IEEE Transactions on Power Electronics, Jg. 36 (2021-09-01), S. 10447-10460 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 1941-0107 (print) ; 0885-8993 (print) |
DOI: | 10.1109/tpel.2021.3061715 |
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