A low-power column-parallel cyclic ADC for CMOS image sensor with capacitance and current scaling
In: Microelectronics Journal, Jg. 105 (2020-11-01), S. 104908-104908
Online
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Zugriff:
This paper presents a power-optimized column-parallel cyclic ADC for CMOS image sensor readout circuits. By separating the capacitor and bias current source and floating them in the circuit, the multiplying digital-to-analog converter (MDAC)'s capacitive load and bias current can be significantly decreased during least significant bit (LSB) quantization, which allows the ADC to reduce power consumption while maintaining a constant conversion rate. The residual quantization characteristic of MDAC makes the input-referred noise produced in LSB quantization relatively small, so the additional noise generated by capacitance scaling can be compensated by increasing the capacitance load of the most significant bit (MSB). A 14-bit two-stage column-parallel cyclic ADC is designed using 0.13-μm technology. The simulation results show that the effective-number-of-bit (ENOB) is 13.54 bit under 0.96-μs sampling rate, and the power consumption of each column is 631 μW. Compared with the traditional structure, the power consumption of ADC is reduced by 35.1%, while the performance remains unchanged.
Titel: |
A low-power column-parallel cyclic ADC for CMOS image sensor with capacitance and current scaling
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Autor/in / Beteiligte Person: | Xu, Jiangtao ; Zhu, Jianian ; Nie, Kaiming |
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Zeitschrift: | Microelectronics Journal, Jg. 105 (2020-11-01), S. 104908-104908 |
Veröffentlichung: | Elsevier BV, 2020 |
Medientyp: | unknown |
ISSN: | 0026-2692 (print) |
DOI: | 10.1016/j.mejo.2020.104908 |
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