High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
In: IEEE Electron Device Letters, Jg. 27 (2006-05-01), S. 383-386
Online
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Zugriff:
This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.
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High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices
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Autor/in / Beteiligte Person: | Kwong, Dim-Lee ; Kumar, Rakesh ; Tung, C.H. ; Agarwal, Ajay ; Yang, R. ; Balasubramanian, N. ; Rustagi, S.C. ; Singh, Navab ; Lo, G. Q. ; Liow, Tsung-Yang ; Lakshmi Kanta Bera |
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Zeitschrift: | IEEE Electron Device Letters, Jg. 27 (2006-05-01), S. 383-386 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2006 |
Medientyp: | unknown |
ISSN: | 0741-3106 (print) |
DOI: | 10.1109/led.2006.873381 |
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