Fault simulation algorithm for transistor single stuck short faults

In this paper an algorithm is developed in Verilog to find out all possible test vectors for testing single stuck short faults in 2-input CMOS nand gate at transistor level. To segregate the faulty circuit from fault free circuit testing is essential. Device is tested by applying test vectors to circuit under test (CUT). If the output response matches exactly with the responses of the fault free circuit for the same test vector, CUT passes the test otherwise declared as faulty circuit. The algorithm is based on the fact that only one fault is present in the circuit at a time. Therefore four different faulty circuits are being simulated along with the fault free circuit. The code is simulated using Xilinx simulator and the identification of all possible test vectors is done by means of waveform generated after simulation.