Dual-Threshold CMOS for Complementary Pass-Transistor Adiabatic Logic with Gate-Length Biasing Techniques

To decrease leakage power dissipations is becoming increasingly important in low-power nanometer circuits because of the increasing subthreshold leakage. This chapter presents a dual-threshold CMOS (DTCMOS) for complementary pass-transistor adiabatic logic (CPAL) circuits with a gate-length biasing technique to reduce subthreshold leakage dissipations. The flip-flops based on two-phase DTCMOS CPAL circuits with gate-length biasing techniques are verified. A traffic light controller is demonstrated at a 45 nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using Hailey Simulation Program with IC Emphasis (HSPICE). Results show that leakage dissipations of the DTCMOS CPAL traffic light controller with the gate-length biasing technique are reduced compared with the basic CPAL one.