3.7 mW 24 GHz LNA with 10.1 dB gain and 4.5 dB NF in 0.18 [micro sign]m CMOS technology

A low-power 24 GHz low-noise amplifier (LNA) with flat and low noise figure (NF) using standard 0.18 µm CMOS technology is demonstrated. The low-power LNA consists of three cascaded common-source stages biased in the weak inversion region. To achieve sufficient gain, a series peaking inductor (LG3) was added to the input terminal of the third stage to boost the gain (simulation shows a 78.9% improvement (from 5.7 to 10.2 dB) at 24 GHz). Flat and low NF was achieved by adopting a slightly under-damped Q-factor for the second-order NF frequency response. Shunt RC feedback in conjunction with a low-Q RL load were adopted in the third stage to achieve excellent output impedance matching. The 24 GHz LNA achieved S21 of 10.1 dB and NF of 4.5 dB with a power dissipation (PDC) of only 3.7 mW, the lowest PDC ever reported for a 24 GHz-band CMOS LNA with S21 greater than 10 dB.