Performance enhanced op-amp for 65nm CMOS technologies and below

Multistage operational amplifiers suitable for nanometer-scale CMOS technologies and low-voltage applications are described. The low intrinsic gain of transistors is compensated for with cascade of single-stage amplifiers. Techniques for compensations are revisited and the optimal solution identified. An example of a novel scheme that achieves 67 dB of DC gain, 320 MHz of bandwidth and 61 degrees of phase margin is presented. The power consumption is as low as 0.24 mW with a slew rate of 84.5 V=µ s. The CMOS technology is 65 nm; the design uses only minimum channel length transistors.